// module name: DFF
// author: yangtao2019
// date: 2021.07.11

`timescale 1ns / 1ps

module DFF
#(
    parameter WIDTH = 64
)
(
    input clk, arst,
    input[WIDTH-1:0] D,
    output reg[WIDTH-1:0] Q 
);

    // main part: D-filp-flop-like structure
    always @ (posedge clk or posedge arst) begin
        if (arst)
            Q <= 0;
        else
            Q <= D;
    end

endmodule


